The present invention relates to technology for fabricating a semiconductor device, and more particularly, to a semiconductor device and a method for fabricating the same, capable of securing a data retention time desired in the semiconductor device employing 40 nm manufacturing processes.
Recently, because of a high degree of integration of a semiconductor device, it has been difficult to secure stable operational characteristics of a transistor. Moreover, as manufacturing processes of a semiconductor memory device has rapidly decreased to 40 nm manufacturing processes, the size of a cell transistor is also reduced and thus characteristic margins such as a threshold voltage, a current drivability, an operational speed and a data retention time margin are reaching their limitations.
In particular, in a semiconductor memory device where 40 nm manufacturing processes is applied, it has been difficult to secure the desired data retention time margin with appropriate characteristic margins. This is because gate induced drain leakage (GIDL) occurring in a region where a source and drain region overlaps with a gate electrode rapidly increases as the size of the transistor is reduced.
This GIDL due to the tunneling of electrons generated between the source and drain region and the gate electrode may be removed/reduced by reducing the region where the source and drain region overlaps with the gate electrode through the forming of a shallow junction of the source and drain region, or increasing the thickness of a gate insulation layer disposed between the source and drain region and the gate electrode. However, as the size of the transistor decreases, the thickness of the gate insulation layer is also inevitably reduced. Therefore, it becomes difficult to maintain an adequate thickness of the gate insulation layer and prevent the increase of a leakage current due to the GIDL. Accordingly, in order to prevent the increase of the leakage current due to the GIDL, the source and drain region are desired to be formed to have the shallow junction, thereby reducing the region where the source and drain region overlaps with the gate electrode. For this purpose, a method for applying an elevated source/drain (ESD) structure to a transistor is introduced.
The ESD structure is formed by a method for forming a source and drain region having a shallow junction. That is, after forming an epitaxial layer only in a region where the source and drain region is to be formed through an epitaxial growth method, e.g., a selective epitaxial growth (SEG) method, the source and drain region having the shallow junction is formed by doping impurities into the epitaxial layer.
FIGS. 1A and 1B illustrate a method for fabricating a conventional semiconductor device. Herein, FIGS. 1A and 1B illustrate a semiconductor device having a channel with a saddle fin structure.
Referring to FIG. 1A, a first recess pattern 14 is formed in an active region 13 by etching a substrate 11 where the active region 13 is defined by an isolation layer 12. A second recess pattern 15 is formed in the isolation layer 12 to form the saddle fin structure where a lower surface and a lower side of the first recess pattern 14 protrude.
Then, after forming a gate 19 to fill the first recess pattern 14 and the second recess pattern 15, a gate spacer 20 is formed on sidewalls of the gate 19, wherein the gate 19 includes a gate insulation layer 16, a gate electrode 17 and a gate hard mask layer 18 that are sequentially stacked.
Subsequently, after forming an inter-layer insulation layer 21 filling a space between the gates 19 over the entire surface of the substrate 11, a contact hole 22 is formed to expose a surface of a portion of the substrate 11 where a source and drain region is to be formed by performing a self aligned contact (SAC) etch process. Then, an epitaxial layer 23 partially filling the contact hole 22 is formed using an epitaxial growth method.
Referring to FIG. 1B, the source and drain region 24 is formed to have a shallow junction by doping impurities into the epitaxial layer 23.
However, in the semiconductor device where 40 nm manufacturing processes is applied, since an area of the substrate 11 exposed after the SAC etching process is relatively narrow and the exposed area of the substrate 11 is not uniform over the substrate 11, it is relatively difficult to form the epitaxial layer 23 using the epitaxial growth method and it takes a considerable amount of time to form the epitaxial layer 23.
Furthermore, the epitaxial layer 23 is not uniformly formed over the substrate 11, referring to a portion indicated by a reference numeral A in FIG. 1A, or the epitaxial layer 23 is formed abnormally, referring to a portion indicated by a reference numeral B in FIG. 1A, by the damage 25 of the substrate 11 and by-products 26 generated during the SAC etch process.
That is, in case the epitaxial layer 23 is not uniformly formed over the substrate 11, it is difficult to adjust a junction depth of the source and drain region 24. Accordingly, as can be seen from a portion indicated by a reference numeral C in FIG. 1B, the junction depth of the source and drain region 24 is increased and thus it is impossible to form an elevated source/drain structure. Meanwhile, in case the epitaxial layer 23 is abnormally formed, as can be seen from a portion indicated by a reference numeral D in FIG. 1B, the source and drain region 24 is also abnormally formed, so that the performance of the semiconductor device is deteriorated or the semiconductor device does not normally operate.
Moreover, in the process of forming the epitaxial layer 23 using the epitaxial growth method, the high temperature of approximately 700° C. to approximately 800° C. is desired in general and thus there occur thermal stress and out-diffusion of impurities pre-doped before the epitaxial layer 23 is formed, which may result in the deterioration of the performance of the semiconductor device.